This is the sixth in a series of computer science and electronics lessons about latches and flip-flops. In particular, this video covers the JK flip flop, which is one of the most versatile flip flops. It is widely used in shift registers, ripple counters, event detectors, frequency dividers, and more. The video begins with a review of the active high, NOR based, SR latch and the active low, NAND based, SR latch. It examines the main limitation of the SR latch, namely an invalid combination of inputs which makes its behaviour unpredictable. The video then covers the JK Latch which addresses the invalid input problem by interlocking the inputs and outputs, thereby allowing the JK latch to toggle from one state to the other. The rising edge triggered JK flip flop is then described by means of a timing diagram and a truth table. The lesson concludes with a description of a modified version of the JK flip flop, namely the Toggle type flip flop, or T type flip flop.

Chapters:
00:00 Introduction to the JK Flip Flop
00:46 Review of the NOR based SR latch
01:50 Invalid state of the NOR based SR latch
03:26 Review of the NAND based SR latch
04:14 Invalid state of the NAND based SR latch
04:50 NOR based JK Latch
07:10 NAND based JK Latch
08:46 Gated JK Latch
10:50 Level triggered JK Flip Flop
11:24 Edge triggered JK Flip Flop
13:18 T Type Flip Flop