This is the second in a series of computer science videos about latches and flip-flops. These bi-stable combinations of logic gates form the basis of computer memory, counters, shift registers, and more. In particular, this video covers the gated set-reset latch. It begins by reviewing the ungated SR latch, including the risk of making both inputs high at the same time, and then goes on to show how SR latches that were built using NOR gates, and SR latches that were built using NAND gates, can be modified to make gated SR latches. Timing diagrams are also introduced, as a means of describing the behaviour of a latch. The videos that follow this one build upon the principles covered here and include the gated D latch, edge triggered pulse latches and the master slave D type flip-flop.