#vlsi #academy #sta #setup #hold #VLSI #electronics #semiconductor #cell #delay
This video describes the timing exceptions present in a design in detail with example, brought to you by @VLSIAcademyhub . This is multipart video, and we have explained the false path in this case. Please watch video and let us know your feedback in comments section.
setup hold timing fixes video link :
https://youtu.be/0wER0TjAHwY
https://youtu.be/LmxSm2Co_SY