#vlsi #academy #sta #setup #hold #VLSI #electronics #semiconductor #cell #delay
This video describes how to do timing fixes (setup and hold).
This is a 2 part video, first video is describing what commonly causes setup violations in path and how can we fix it. This is second part of video for hold violations fixes.
All sort of examples are taken to describe it properly.

Video link for understanding intra timing paths (reg2reg type)
https://youtu.be/YlX5a73-RTw
previous video link for setup timing fixes
https://youtu.be/0wER0TjAHwY